1. Field of the Invention
The present invention relates to line interface devices, and, in particular, to a CMOS driver meeting the standard for Backplane Transceiver Logic (BTL) that is used for interfacing CMOS digital circuits to transmission lines.
2. Description of the Related Art
Digital systems typically include several Very Large Scale Integrated (VLSI) circuits that cooperate and communicate with one-another to perform a desired task. FIG. 1 illustrates a typical digital system. The VLSI circuits are mounted on several circuit boards that are referred to as "daughter boards". Each daughter board may accommodate several VLSI circuits. In turn, the daughter boards are received by a "mother board" that has circuitry for facilitating communication between the individual daughter boards.
The individual VLSI circuits are interconnected for binary communication by transmission mediums. The transmission mediums are generally collected together to form buses. The number, size and types of buses that are used in a digital system may be designed for general-purpose applications or according to a more specific, industry standard data-communications configuration. One such industry standard is the so-called IEEE 896.1 Futurebus+ standard. The Futurebus+ standard provides a protocol for implementing an internal computer bus architecture.
FIG. 1 illustrates the hierarchy of the several different bus levels utilizable in a Futurebus+ system. A "component level bus" is used to interconnect the several VLSI circuits that are located on a single daughter board, and a "backplane bus" is used to interconnect the VLSI circuits of one daughter board to the VLSI circuits of another daughter board. Thus, a component level bus is constructed on each daughter board, and a backplane bus is constructed on the mother board.
The transmission mediums which form the component and backplane buses are typically traces which are formed on the printed circuit board (PCB) substrates of the daughter and mother boards. Microstrip traces and strip line traces can be employed to form transmission lines having characteristic impedances on the order of about 50.OMEGA.-70.OMEGA.. Such transmission lines usually have their opposite ends terminated in their characteristic impedance. Because of these parallel resistive terminations, the effective resistance of the transmission line may be as low as 25.OMEGA.-35.OMEGA..
Data transceivers (TRANSmitter/reCEIVER) are used to interface the VLSI circuits to the transmission medium. FIG. 2 illustrates the positioning of a data transceiver between the backplane bus of a Futurebus+ system and the data bus of a VLSI circuit to facilitate communications between the VLSI circuit and the rest of the digital system.
A data transceiver is a read/write terminal capable of transmitting information to and receiving information from the transmission medium. A transceiver typically includes a line driver stage (or simply "driver") and a receiver stage (or simply "receiver"). The common purpose of transmission line drivers and receivers is to transmit data quickly and reliably through a variety of environments over electrically long distances. This task is complicated by the fact that externally introduced noise and ground shifts can severely degrade the data.
Drivers amplify digital signal outputs from the VLSI circuitry so that the signals can be properly transmitted on the transmission medium. Receivers are typically differential amplifiers that receive signals from the transmission medium and provide outputs to the VLSI circuitry that are representative of digital information received from the medium.
Conventional drivers usually include level shifting capability to provide compatibility with different integrated circuit technologies. Specifically, before a driver transmits a signal across a transmission medium, the driver changes the nominal voltage swing (or the "dynamic signal range") utilized by the VLSI circuitry, e.g., CMOS, TTL, ECL, etc., to a different voltage swing that is utilized by the transmission medium. Thus, a driver not only amplifies a digital signal, but it changes the nominal voltage swing of the signal as well.
A different nominal voltage swing is normally used when transmitting data across a transmission medium in order to conserve power. Specifically, the power internally dissipated by the driver is proportional to the nominal voltage swing of the binary signal it applies to the transmission line. Therefore, power dissipation is reduced if the driver transmits a signal having a relatively small voltage swing over the transmission line.
It has become common for signals to be transmitted over transmission lines at BTL (Backplane Transceiver Logic) signal levels. The signal level standard is denoted "Backplane" because BTL has been used primarily in the backplane buses of mother boards. Because the nominal voltage swing of BTL is 1.0 Volt (logic low) to 2.1 Volts (logic high), power dissipation is less than it would be if the signals were transmitted over the transmission lines at CMOS (0 Volts to 3.3 Volts, or, 0 Volts to 5.0 Volts) or TTL (0 volts to 3.5 Volts) signal levels.
Signals have also been transmitted over transmission lines at the so-called "GTL" signal levels (See U.S. Pat. No. 5,023,488 to Gunning). The nominal voltage swing of GTL is approximately 0.3 Volts (logic low) to 1.2 Volts (logic high).
FIG. 3 illustrates a conventional BTL driver 20. The driver 20 receives CMOS level signals at input V.sub.IN and outputs BTL level signals at output V.sub.OUT. The driver 20 is implemented with bipolar transistors Q1, Q2, Q3, Q4, and Q5. Bipolar technology is attractive for implementing I/O devices, such as line or bus drivers, because of its unique high current gain characteristic. High current gain is important in a bus system such as future bus backplane because the driver 20 must be capable of driving the transmission line in both unloaded and loaded conditions.
In order to determine the current I.sub.DU that must be generated by the driver 20 to drive an unloaded transmission line, the impedance Z.sub.U of the unloaded transmission line must be considered. As mentioned above, both ends of the bus are typically terminated with bus characteristic impedance Z.sub.o (typically 50 .OMEGA.). Thus, because of the parallel bus end terminations, the impedance Z.sub.U of the unloaded backplane bus is approximately: ##EQU1## In order for the driver 20 to transmit data over the unloaded backplane bus, the driver 20 should be capable of transmitting a current I.sub.DU approximately equal to: ##EQU2##
In order to determine the current I.sub.DL that must be generated by the driver 20 to drive a loaded transmission line, the impedance Z.sub.L of the loaded transmission line must be considered. When the backplane bus is uniformly loaded with the capacitance of plugged-in daughter boards at frequent intervals, the impedance Z.sub.L of the loaded backplane bus is given by: ##EQU3## For a system such as IEEE 896 which has 10 slots per foot, C.sub.L is approximately equal to: EQU C.sub.L =10.times.10=100 pF/ft;
and, Z.sub.L is approximately equal to: ##EQU4## The drive current required to drive the loaded backplane bus is approximately equal to: ##EQU5##
Therefore, the BTL driver 20 must generate approximately 40 mA to drive an unloaded backplane bus and approximately 65 mA to drive a loaded backplane bus. Due to its high current gain, the bipolar NPN transistor Q1 seems particularly suited to be the driving device of the BTL driver 20.
Although the BTL driver 20 is capable of generating the current required to drive a backplane bus, it suffers from a number of disadvantages due to its bipolar construction.
First, because of the large collector capacitance of transistor Q1, a blocking schottky diode D1 is required in order to reduce the driver 20 output capacitance to less than 2.0 pF.
Second, the driver 20 output V.sub.OUT has a very fast rising and falling edge. Without control, the fast rising and falling edge can create ground bouncing, output over/under shoot, and cross-talk between bus conductors. These adverse effects can significantly reduce a receiver's noise margin. In order to control the adverse effects that can be caused by a fast rising and falling edge, Futurebus+ specifies a minimum rise-time t.sub.r and fall-time t.sub.f 1 nano-second measured between 20% to 80% of the voltage swing levels.
In order to meet the Futurebus+ specifications with respect to t.sub.r and t.sub.f, the BTL driver 20 uses a miller capacitor C.sub.M between the collector of transistor Q1 and the base of transistor Q2 to increase t.sub.f. Specifically, t.sub.f is given by: ##EQU6## where I.sub.bQ2 is the base current of transistor Q2. Similarly, the BTL driver 20 uses the capacitance C.sub.ob at the collector-base junction of transistor Q1 to control t.sub.r. Specifically, t.sub.r is given by: ##EQU7## where I.sub.bQ1 is the base current of transistor Q1. The problem with controlling t.sub.f and t.sub.r in this manner, however, is that both I.sub.bQ2 and I.sub.bQ1 are supply voltage and temperature dependant. When temperature decreases and the supply voltage increases, I.sub.bQ2 and I.sub.bQ1 both increase which results in a decrease in t.sub.r and t.sub.f. Thus, the t.sub.r and t.sub.f of the BTL driver 20 are difficult to control during variations in temperature and supply voltage. If not controlled, t.sub.r and t.sub.f could fall below the Futurebus+ minimum specifications.
Another disadvantage of the bipolar BTL driver 20 is the skew between its turn-on and turn-off delay. When temperature increases and supply voltage increases, the increase in the base turn-on current I.sub.bQ1ON and current gain of transistor Q1 significantly increases transistor Q1's base over-drive. An increase in temperature of 100.degree. C. can increase the base turn-on current I.sub.bQ1ON and current gain of transistor Q1 by 100%. Such an increase in transistor Q1's base over-drive causes t.sub.r, and thus, turn-on time, to get much shorter.
However, the increase in the base turn-on current I.sub.bQ1ON of transistor Q1 due to the temperature and supply voltage increases causes more storage charge to accumulate in transistor Q1's collector and base region. The accumulation of storage charge causes the base turn-off current I.sub.bQ1OFF (V.sub.BEQ1 /R1) of transistor Q1 to decrease, and the decrease in I.sub.bQ1OFF causes t.sub.f and the turn-off time of transistor Q1 to be very long. Therefore, the skew between the turn-on and turn-off times tends to get worse as temperature and supply voltage increase.
Other disadvantages of the BTL driver 20 due to its bipolar implementation are high power dissipation and the inefficiency of large scale integration due to lower gate density and higher cost. These disadvantages would also be present in a BiCMOS implementation.
Thus, there is a need for a BTL driver that overcomes the disadvantages of the conventional bipolar BTL driver discussed above.